Built by a Hardware Engineer for Hardware Engineers
SiliconCraft AI is an early-stage founder project focused on AI-assisted RTL review. Started in October 2026 by Vo Hoang Nguyen in Vietnam, it is bootstrapped, independently developed, and not yet incorporated.
Vo Hoang Nguyen — Solo Founder
While developing RISC-V CPU and FPGA projects, I repeatedly traced pipeline hazards, forwarding paths, reset behavior, and RTL bugs across source code and simulation results. SiliconCraft AI grew from the need for careful, hardware-specific RTL and microarchitecture review.
General-purpose AI tools could explain pieces of code, but often lacked the hardware-specific context I needed for RTL review. Repeated debugging loops around pipeline control, load-use hazards, resets, widths, and verification assumptions led me to build a workspace focused on digital hardware reasoning.
My background is in Electronics / Digital Hardware Engineering. Public projects include a five-stage RISC-V core with hazard and forwarding control, FPGA work, and an asynchronous FIFO with Gray-coded pointers, reset synchronization, testbenches, and assertions.
Current stage: founder/internal testing, with no external users yet. The next focus is onboarding RTL and FPGA engineers, collecting feedback, and measuring review usefulness and false positives.
Engineering Principles:
Transparent RTL Data Handling
RTL is sent to Anthropic for review. Full-source storage is disabled by default; saved reports can contain source excerpts. Provider data handling follows the configured service agreement.
No Overpromising
We clearly mark available features versus active roadmap specs. We never present unfinished capabilities as completed tools.
Complements Standard EDA
AI findings support engineering review before simulation and synthesis. Tool execution and compatibility checks remain outside the current workflow.