Founder-led Testing for RTL & FPGA Engineers

Design. Verify. Debug RTL with AI.

AI-assisted RTL review for engineers working with Verilog, SystemVerilog, FPGA, and RISC-V designs.

Founder-led testing. AI analysis availability depends on this environment; real RTL examples are available to explore.

illustrative_hazard_example.sv— SystemVerilog

Sample Analysis

// 5-Stage RISC-V Pipeline Hazard Control UnitLine 26:1

1	module hazard_unit (
2	input logic [4:0] rs1_ex, rs2_ex,
3	input logic [4:0] rd_mem, rd_wb,
4	input logic reg_write_mem, reg_write_wb,
5	input logic mem_to_reg_ex, // Load in EX
6	output logic [1:0] forward_a_ex, forward_b_ex,
7	output logic stall_if_id
8	);
9	// Forwarding logic to EX stage
10	always_comb begin
11	forward_a_ex = 2'b00; forward_b_ex = 2'b00;
12	if (reg_write_mem && (rd_mem != 0) && (rd_mem == rs1_ex))
13	forward_a_ex = 2'b10; // EX hazard
14	// Load-Use Hazard: FIXME unhandled stall!
15	assign stall_if_id = 1'b0; // Bug: Always 0
16	endmodule

EDA execution: Not runRISC-V RV32I

Sample Analysis

REVIEW EXAMPLE

Potential Load-Use Data Hazard Detected

The constant stall output needs review in pipeline context. Load destination, dependent decode operands, validity and memory latency are needed to assess load-use handling.

Pipeline Forwarding Checks:

EX/MEM Forwarding MuxNOT VERIFIED

MEM/WB Forwarding MuxNOT VERIFIED

Load-Use Pipeline StallCONTEXT NEEDED

Integration Context Needed:No automatic patch

Identify the load destination and dependent source stages.
Then verify stalls, bubbles, forwarding and instruction validity.

Illustration: not a live result

The Hardware Bottleneck

Digital hardware development is held back by manual verification loops.

Hardware engineers can spend substantial time debugging simulation traces and building repetitive verification infrastructure.

Reviewing RTL with Hardware Context

A useful review depends on cycle behavior, signal widths, state ownership, and integration assumptions that may span multiple modules.

Painstaking RTL & Simulation Debugging

Tracing load-use hazards, forwarding paths, and reset behavior often requires repeated review of source code and simulation results.

Repetitive Testbench & Assertion Writing

Hand-crafting UVM-style stimulus generators, clock drivers, and SVA assertions for every sub-module slows down turn-around times for FPGA and ASIC prototypes.

AI-Native Hardware Engineering Workspace

Review RTL earlier, with hardware-specific context.

SiliconCraft starts with AI-assisted RTL review. Other workflow capabilities are previews or roadmap items.

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Analyze Verilog and SystemVerilog for logic bugs, synthesis concerns, reset behavior, timing risks, and coding standard violations.

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Explore a sample log-review workflow. Live simulator-log analysis and EDA tool execution are not available.

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RISC-V / CPU Pipeline Analysis

Reason about 5-stage CPU pipelines, load-use data hazards, forwarding multiplexers, branch target buffers, and hazard control units.

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Extract register maps, signal definitions, and protocol rules from hardware datasheets and technical specifications.

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Interpret critical paths, LUT/FF utilization reports, clock domain crossings (CDC), and setup/hold time violations.

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Built Against Real Hardware Designs

SiliconCraft AI is developed and evaluated using real RTL modules from RISC-V processors, FPGA subsystems, CDC logic, and verification environments.

RISC-V 5-stage CPU

Hazard detection, CSR dependencies and ALU execution from the founder's RV32IM core.

riscv-rv32im-core ↗

Asynchronous FIFO / CDC

Independent read/write clocks, Gray-coded pointer crossings and per-domain reset synchronization.

Asynchronous-FIFO ↗

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Assertion and testbench sources provide context for FIFO behavior and verification questions. The website does not execute them.

async_fifo_sva.sv ↗

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Test the Copilot on Real SystemVerilog Snippets

Explore local snapshots from the founder’s hardware projects. AI analysis requires sign-in and a configured backend.

Founder-led testing. AI analysis availability depends on this environment; real RTL examples are available to explore.

Sign-in required. LLM review only; no EDA tools run. Source is sent to Anthropic. Accepted attempts count toward usage.

Interactive RTL Copilot LaboratoryDemo

Real RTL Examples

Load a local source snapshot, then run analysis when ready.

RISC-V Hazard Unit

Real RTL

Pipeline hazard detection and stall control from a real 5-stage RISC-V core.

riscv-rv32im-core

RISC-VSystemVerilogPipelineHazard Detection

View Source on GitHub

Asynchronous FIFO

Real RTL

Clock-domain crossing FIFO using Gray-coded pointers and synchronizers.

Asynchronous-FIFO

CDCFIFOSystemVerilogClock Domains

View Source on GitHub

RV32 ALU / Execution Logic

Real RTL

Combinational execution logic from a real RV32IM processor.

riscv-rv32im-core

RISC-VALURTLSystemVerilog

View Source on GitHub

RTL Source EditorSystemVerilog · hazard_unit.sv

// Combinational ID-stage hazard detector.
//
// A load in ID/EX cannot forward to its immediate consumer; all other GPR RAW
// dependencies use EX forwarding. CSR readers also wait for conflicting
// writers in ID/EX or EX/MEM. A MEM/WB writer commits before the reader reaches
// EX, so it requires no additional stall.
module hazard_unit (
  input  logic                         id_valid_i,
  input  logic [4:0]                   id_rs1_i,
  input  logic [4:0]                   id_rs2_i,
  input  logic [11:0]                  id_csr_addr_i,
  input  wire rv32_pkg::decode_ctrl_t  id_ctrl_i,

input  wire rv32_pkg::id_ex_t        id_ex_i,
  input  wire rv32_pkg::ex_mem_t       ex_mem_i,
  input  wire rv32_pkg::mem_wb_t       mem_wb_i,

output logic                         load_use_o,
  output logic                         csr_dep_o,
  output logic                         stall_id_o
);

import rv32_pkg::*;

logic id_ex_is_load;
  logic id_ex_csr_writer;
  logic ex_mem_csr_writer;
  logic csr_dependency;
  logic mret_dependency;
  logic minstret_dependency;

function automatic logic raw_match(
    input logic      producer_valid,
    input logic      producer_writes,
    input reg_addr_t producer_rd,
    input logic      consumer_uses,
    input reg_addr_t consumer_rs
  );
    begin
      raw_match = producer_valid && producer_writes && (producer_rd != 5'd0) && consumer_uses && (producer_rd == consumer_rs);
    end
  endfunction

// CSRRW[I] always writes; CSRRS/RC[I] suppress writes for a zero mask.
  function automatic logic csr_command_writes(
    input csr_cmd_e  command,
    input reg_addr_t source
  );
    begin
      unique case (command)
        CSR_RW,
        CSR_RWI: csr_command_writes = 1'b1;

CSR_RS,
        CSR_RC,
        CSR_RSI,
        CSR_RCI: csr_command_writes = (source != 5'd0);

default: csr_command_writes = 1'b0;
      endcase
    end
  endfunction

// Low/high counter CSRs alias one 64-bit state: writing either half suppresses
  // that edge's implicit update and may affect the other half across a carry.
  // Other implemented CSRs conflict only on an exact address match.
  function automatic logic csr_addresses_conflict(
    input csr_addr_t consumer,
    input csr_addr_t producer
  );
    begin
      unique case (consumer)
        CSR_MCYCLE,
        CSR_MCYCLEH: begin
          csr_addresses_conflict = (producer == CSR_MCYCLE) || (producer == CSR_MCYCLEH);
        end

CSR_MINSTRET,
        CSR_MINSTRETH: begin
          csr_addresses_conflict = (producer == CSR_MINSTRET) || (producer == CSR_MINSTRETH);
        end

default: csr_addresses_conflict = (consumer == producer);
      endcase
    end
  endfunction

always_comb begin
    id_ex_is_load = id_ex_i.valid && !id_ex_i.exc.valid && id_ex_i.ctrl.reg_write && (id_ex_i.ctrl.mem_cmd == MEM_LOAD);

load_use_o = 1'b0;
    if (id_valid_i) begin
      load_use_o = raw_match(
        id_ex_is_load,
        id_ex_i.ctrl.reg_write,
        id_ex_i.rd,
        id_ctrl_i.uses_rs1,
        id_rs1_i
      ) || raw_match(
        id_ex_is_load,
        id_ex_i.ctrl.reg_write,
        id_ex_i.rd,
        id_ctrl_i.uses_rs2,
        id_rs2_i
      );
    end

id_ex_csr_writer = id_ex_i.valid && !id_ex_i.exc.valid && csr_command_writes(id_ex_i.ctrl.csr_cmd, id_ex_i.rs1);

ex_mem_csr_writer = ex_mem_i.valid && !ex_mem_i.exc.valid && ex_mem_i.csr_write;

// Stall only for an older writer to the same CSR state, avoiding false
    // dependencies without weakening RAW ordering.
    csr_dependency = id_valid_i && (id_ctrl_i.csr_cmd != CSR_NONE) && ((id_ex_csr_writer && csr_addresses_conflict(id_csr_addr_i, id_ex_i.insn[31:20]))
                       || (ex_mem_csr_writer
                           && csr_addresses_conflict(id_csr_addr_i, ex_mem_i.csr_addr)));

// MRET reads only mepc and waits only for an older mepc writer.
    mret_dependency = id_valid_i && id_ctrl_i.is_mret && ((id_ex_csr_writer && (id_ex_i.insn[31:20] == CSR_MEPC)) || (ex_mem_csr_writer && (ex_mem_i.csr_addr == CSR_MEPC)));

// Drain older stages before reading minstret[h], so all preceding
    // retirements are visible in program order.
    minstret_dependency = id_valid_i && (id_ctrl_i.csr_cmd != CSR_NONE) && ((id_csr_addr_i == CSR_MINSTRET) || (id_csr_addr_i == CSR_MINSTRETH))
                        && ((id_ex_i.valid && !id_ex_i.exc.valid) || (ex_mem_i.valid && !ex_mem_i.exc.valid));

csr_dep_o  = csr_dependency || mret_dependency || minstret_dependency;
    stall_id_o = load_use_o || csr_dep_o;
  end

// MEM/WB is intentionally not interlocked: its CSR write becomes visible
  // before the held ID instruction reads that CSR in EX.

endmodule

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Click "Analyze RTL Logic" for an AI review of logic, reset behavior, width handling and timing risks. No EDA tools run.

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Designed for standard HDLs and open-source/commercial EDA toolchains.

Current focus: Verilog and SystemVerilog review. EDA integrations are roadmap targets; no tool execution or compatibility certification is provided.

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Early access

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Built by a Hardware EngineerSolo Founder

Why I am building SiliconCraft AI

While developing RISC-V CPU and FPGA projects, I repeatedly traced pipeline hazards, forwarding paths, reset behavior, and RTL bugs across source code and simulation results. SiliconCraft AI grew from the need for careful, hardware-specific RTL and microarchitecture review.

General-purpose AI tools could explain pieces of code, but often lacked the hardware-specific context I needed for RTL review. Repeated debugging loops around pipeline control, load-use hazards, resets, widths, and verification assumptions led me to build a workspace focused on digital hardware reasoning.

Vo Hoang Nguyen•Solo Founder & Hardware Engineer

Build better hardware with an AI engineering copilot.

Explore real RTL examples and help shape AI-assisted review. Founder/internal testing only; the first external engineers are yet to be onboarded.